1. Field of the Invention
This invention relates to a microcomputer capable of monitoring internal memory, and in particular relates to a microcomputer capable of monitoring internal memory without halting microcomputer operation.
2. Description of the Related Art
A microcomputer has a CPU, internal memory such as RAM and ROM, peripheral resources having prescribed functions, and other components, connected by an internal bus. The CPU sequentially executes programs in the ROM, and when necessary writes data in the RAM and controls outside devices to be controlled via peripheral resources. As the controlled devices, for example, the combustion in an automobile engine or the vehicle wiper blades may be controlled.
In the stage of development of such a microcomputer, the microcomputer is connected to the controlled device, a program is executed, and an evaluation is performed to determine whether the program can appropriately perform the control as the initially desired function. In this case, in order to halt and restart the program at an arbitrary address of the program, and to monitor data at an arbitrary address of the internal memory, a microcomputer for evaluation, equipped with a debug support unit (DSU), is employed.
It is desirable that a microcomputer for evaluation have various evaluation functions for use in program evaluation and debugging. One of these is a function to access internal memory without halting CPU operation. For example, it has been proposed that, in addition to memory which stores a program to be executed by the CPU for evaluation, memory to store conversion data is provided, conversion data is written to this memory from a control CPU, and the target for access by the CPU is switched from the program memory to the conversion data memory with a certain timing so that the CPU for evaluation is caused to access the conversion data storage memory. Such an emulator is for example described in Japanese Patent Laid-open Publication No. 2001-101026 (Laid-open Publication Date: Apr. 13, 2001).
The emulator described in this Japanese Patent Laid-open Publication No. 2001-101026 is characterized in that a prescribed address in the program memory is switched to the conversion data memory, so that any desired parameters or commands are provided to the CPU, without halting execution of the program of the CPU for evaluation. By this means, desired modifications can be made to the control operation resulting from program execution, and the convenience of debugging or evaluation can be further improved. However, in this Japanese Patent Laid-open Publication No. 2001-101026 there is no description of monitoring of data in internal memory.
In a microcomputer for evaluation equipped with a conventional DSU, the CPU accesses internal memory via an internal bus during program execution, therefore access to the internal memory by the DSU is limited. Hence in order to monitor data in internal memory via a DSU, the DSU supplies a memory access request to the CPU, acquires the bus access rights from the CPU, and accesses the internal memory via the internal bus. Hence in order for the DSU to monitor data in internal memory, the CPU bus access operation must be temporarily halted, and further, in order to acquire bus rights from the CPU, an arbitration procedure extending over a prescribed cycle is necessary; as a consequence, the DSU cannot easily read data from internal memory with arbitrary timing.